As the semiconductor industry has continued to progress toward ever smaller devices, complementary metal-oxide-semiconductor (CMOS) circuits have become increasingly more highly integrated, and the individual devices which are combined to form CMOS circuits have become increasingly smaller. In some instances, the scaling down of these devices has created a need for new technologies, as existing technologies have run into fundamental limitations that prevent them from being scaled down any further.
For example, the use of polysilicon gates in the semiconductor industry is widespread. Polysilicon gates are commonly used in conjunction with silicon dioxide (SiO2) as a gate oxide or gate dielectric. However, when gate oxides are scaled down to thicknesses of less than about 20 angstroms, gate leakage currents, which are determined by quantum-mechanical direct tunneling through the gate oxide, reach intolerably high levels. Also, the scaling down of SiO2-based gate oxides below these thicknesses is inhibited by dopant diffusion from the polysilicon gates, since the resulting thinner gate oxide is significantly more vulnerable to dopant penetration.
Metal gates have emerged as a solution to the aforementioned problems. The use of metal gates blocks dopant penetration and eliminates the poly depletion effect, while allowing the same electrical performance to be obtained, even with a thicker gate oxide. Typical poly depletion increases the electrical equivalent thickness of the gate oxide by 4-6 angstroms. Hence, by eliminating the poly depletion region, the use of metal gates allows gate oxides to remain 4-6 angstroms thicker, thus allowing the leakage current to be reduced by one to two orders of magnitude as compared to a polysilicon gate.
The leakage current can be further reduced by using gate dielectrics that have higher permittivity values or dielectric constants (K) than silicon dioxide. When such dielectric films, which are referred to as high-K dielectric films, are used as gate dielectrics, the physical thickness of the gate dielectric can be larger, while the electrical thickness is equivalent to SiO2. This allows the dielectric layer to be scaled for compatibility with the other reduced feature sizes.
While the use of metal gates in conjunction with high-K dielectric films has many advantages and has helped to address some of the aforementioned scalability issues, it also presents problems of its own. In particular, the use of metal gates has been found to introduce metal contaminants into the fabrication line. The presence of such contaminants can seriously degrade the performance characteristics of semiconductor devices. Although manufacturing protocols have been designed to prevent such cross-contamination, these protocols typically require designated tools or extra cleaning and monitoring steps, and hence add significant processing time and cost to the manufacture of semiconductor devices.
There is thus a need in the art for a method for making semiconductor devices with metal gate structures and other conductor layers that reduces or eliminates the occurrence of metal contaminants in the manufacturing line without adding significantly to the cost of the process. There is further a need in the art for such a method which can be used to make semiconductor devices having metal gate structures with high-K dielectric films. These and other needs are met by the devices and methodologies described herein.